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Patidar, Hemant
- Failure Correction of Linear Array Antenna with Multiple Null Placement Using Cuckoo Search Algorithm
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Authors
Affiliations
1 Department of Electronic and Computer Engineering, Caledonian College of Engineering, OM
2 Department of Electronics and Communication Engineering, National Institute of Technology, Durgapur, IN
1 Department of Electronic and Computer Engineering, Caledonian College of Engineering, OM
2 Department of Electronics and Communication Engineering, National Institute of Technology, Durgapur, IN
Source
ICTACT Journal on Communication Technology, Vol 5, No 1 (2014), Pagination: 877-881Abstract
The influence of evolutionary algorithms enhanced its scope of getting its existence in almost every complex optimization problems. In this paper, cuckoo search algorithm, an algorithm based on the brood parasite behavior along with Levy weights has been proposed for the radiation pattern correction of a linear array of isotropic antennas with uniform spacing when failed with more than one antenna element. Even though deterioration produced by the failure of antenna elements results in various undesirable effects, consideration in this paper is given to the correction of side lobe level and null placement at two places. Various articles in the past have already shown that the idea to correct the radiation pattern is to alter the amplitude weights of the remaining unfailed elements, instead of replacing the faulty elements. This approach is made use of modifying the current excitations of unfailed elements using cuckoo search algorithm such that the resulting radiation pattern is similar to the unfailed original pattern in terms of side lobe level and null placement at two places. Examples shown in this paper demonstrate the effectiveness of this algorithm in achieving the desired objectives.Keywords
Array Failure Correction, Linear Array, Cuckoo Search Algorithm, Side Lobe Level, Multiple Null Placement.
- QPSO for Failure Correction of Linear Array Antenna Including Wide Null Placement
Abstract Views :183 |
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Authors
Affiliations
1 Department of Electrical and Computer Engineering, Caledonian College of Engineering, OM
2 Department of Electronics and Communication Engineering, National Institute of Technology, Durgapur, IN
1 Department of Electrical and Computer Engineering, Caledonian College of Engineering, OM
2 Department of Electronics and Communication Engineering, National Institute of Technology, Durgapur, IN
Source
ICTACT Journal on Communication Technology, Vol 5, No 3 (2014), Pagination: 959-962Abstract
In this paper, the authors have proposed a method based on Quantum Particle Swarm Optimization (QPSO) algorithm in the context of radiation pattern correction of a linear array of isotropic antennas corrupted with one or more faulty antenna elements. Care is taken to maintain the values of side lobe level and maximum Wide Null Placement of the corrected pattern to be identical to the values of nondefective radiation pattern. This correction is made possible by altering the beam weights of the remaining elements in the array. The advantage of this method is that the necessity of replacement of the faulty elements is eliminated. Simulation is done on the linear antenna array constructed of individual isotropic elements separated by identical inter-element spacing and the results obtained from the simulation depict the effectiveness of the proposed method. This method can also be extended to other array geometries.Keywords
Antenna Array, Failure Correction, Quantum Particle Swarm Optimization, Side Lobe Level, Wide Null Placement.- Comparative Study of Evolutionary Algorithms to Generate Flat-Top Beam Pattern for Synthesis of a Linear Antenna Array
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Authors
Affiliations
1 Department of Electrical and Electronics Engineering, Oriental University, IN
2 Department of Electronics and Communication Engineering, Guru Nanak Institutions, IN
3 Department of Electronics and Communication Engineering, National Institute of Technology, Durgapur, IN
4 Department of Electronics and Communication Engineering, Noida Institute of Engineering and Technology, IN
5 Department of Electronics and Communication Engineering, Anil Neerukonda Institute of Technology and Sciences, IN
1 Department of Electrical and Electronics Engineering, Oriental University, IN
2 Department of Electronics and Communication Engineering, Guru Nanak Institutions, IN
3 Department of Electronics and Communication Engineering, National Institute of Technology, Durgapur, IN
4 Department of Electronics and Communication Engineering, Noida Institute of Engineering and Technology, IN
5 Department of Electronics and Communication Engineering, Anil Neerukonda Institute of Technology and Sciences, IN
Source
ICTACT Journal on Communication Technology, Vol 12, No 3 (2021), Pagination: 2519-2526Abstract
In the present paper three evolutionary algorithms are compared and discussed for synthesizing a linear array of dipole antenna of half-wavelength oriented horizontally. All the dipoles are mutually coupled and designed to radiate the flat-top beam (FTB) pattern including multiple single null steering with little ripple deviation. The adopted evolutionary algorithms are; flower pollination algorithm (FPA), firefly algorithm (FA) and back tracking search algorithm (BSA), respectively. These algorithms are then combined with an efficient Inverse Fast Fourier Transform (IFFT) for reduction in the computation of evaluating time meaningfully. The required synthesis is attained by generating the current amplitudes at 00 and 1800 using binary phase shifters for the antenna array. The performance analysis of key antenna parameters along with the statistical parameters is achieved with the help of the optimization process and compared. In this paper, the MATLAB tool is used as a validation tool and the obtained simulation results are very satisfying and acceptable.Keywords
Antenna Array, Backtracking Search Algorithm, Firefly Algorithm, Flower Pollination Algorithm, Flat-Beam Pattern, Side Lobe Level, Single Null Placement, Ripple, VSWR.References
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- H. Patidar and G.K. Mahanti, “QPSO for Synthesis of Linear Array of Isotropic Antennas to Generate Flat-Top Beam Including Multiple Null Placements”, Proceedings of International Conference on Signal Processing and Communication, pp. 46-50, 2015.
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- Literature Survey On Area Optimization Of Cmos Full Adder Design
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Authors
Affiliations
1 Division of Postgraduate Studies and Research, Oriental University, IN
2 Department of Electronics and Communications Engineering, Oriental University, IN
1 Division of Postgraduate Studies and Research, Oriental University, IN
2 Department of Electronics and Communications Engineering, Oriental University, IN
Source
ICTACT Journal on Microelectronics, Vol 7, No 4 (2022), Pagination: 1241-1244Abstract
In this paper, a novel architecture for a dynamic logic-based full adder is introduced and analyzed. In full adder architecture, the XOR and XNOR gates are commonly employed as basic logic units. In the report, improved XOR and XNOR logic gate topologies are employed to produce a full adder circuit. The envisioned XOR/XNOR gate architecture has a full logic cycle. The suggested adder design is modelled using a traditional 180 nm CMOS technique. The simulated outcomes using the SPICE simulation tool demonstrated that the proposed network has significant advantages in energy loss and efficiency while compared to previously published designsKeywords
MOS Current-Mode Logic (MCML), Ternary Full-Adder (TFA), Low Power, Gate-Diffusion-Input (GDI), Ripple Carry Adder (RCA)References
- S. Malipatil, Vikas Maheshwari and Marepally Bhanu Chandra, “Area Optimization of CMOS Full Adder Design Using 3T XOR”, Proceedings of International Conference on Wireless Communication Signal Processing and Networking, pp. 1-7, 2020.
- Aloke Sahaa, Rakesh Kumar Singh, Pragya Gupta and Dipankar Pal, “DPL-Based Novel CMOS 1-Trit Ternary
- S. Sharmila Devi and V. Bhanumathi, “Design of Reversible Logic based Full Adder in Current Mode Logic Circuits”, Microprocessors and Microsystems, Vol. 76, No. 1, pp. 118, 2020.
- Manan Mewada, Mazad Zaveri, Ratnik Gandhi and Rajesh Thakker, “Transmission Gate and Hybrid Cmos Full Adder Characterization and Power-Delay Product Estimation based on Mathematical Model”, Procedia Computer Science, Vol. 171, pp. 999-1008, 2020.
- S. Akhter, “An Efficient CMOS Dynamic Logic- Based Full Adder”, Proceedings of International Conference on Signal Processing and Communication, pp. 1-8, 2020.
- Harsh Yadav, Amit Kumar Goyal and Ajay Kumar, “Design Analysis and Comparative Study of GDI Based Full Adder Design”, Proceedings of International Conference on Signal Processing and Communication, pp. 991-998, 2020.
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- Analysis And Implementation Of Mac Unit For Different Precisions
Abstract Views :139 |
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Authors
Affiliations
1 Department of Electronics and Communication Engineering, Oriental University, IN
1 Department of Electronics and Communication Engineering, Oriental University, IN
Source
ICTACT Journal on Microelectronics, Vol 7, No 4 (2022), Pagination: 1260-1264Abstract
This paper describes the design of the multiply- Accumulate unit and compares all parameters of the 4-bit, 8-bit, 12-bit, and 16-bit MAC unit. MAC is the basic unit that performs the multiplication operation and addition/accumulation operation. This MAC unit is designed on Vivado HLS software using LUTs at room temperature. These designs are analyzed and simulated by using the Vivado HLS tool and implemented on Zybo Evaluation and Development kit (xc7z020clg400-1).Keywords
MAC unit, LUTs, Power, Delay, and UtilizationReferences
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